An FPGA-in-the-Loop Testbed for MU-MIMO OFDM Beamforming over Ray-Traced Wireless Channels

RESUMO

Wireless networks face ever expanding throughput demands from heterogeneous, high-density user populations, requiring beamforming algorithms that adapt to channel conditions with low latency. Validating such algorithms requires either costly over-the-air testbeds or simulation environments that lack the timing and resource constraints of real hardware, leaving a gap between algorithm design and hardware-realizable deployment. This work presents a hardware-in-the-loop (HIL) testbed that closes that gap by coupling an FPGA-based implementation of OFDM Waveforms with MU-MIMO beamforming to NVIDIA Sionna's ray-tracing channel simulator, enabling a physical base-station architecture to transmit and receive against a Sionna-rendered digital-twin propagation environment in real time. Unlike prior work that validates beamforming algorithms either purely in simulation or on full RF testbeds, this architecture allows beamforming logic running on actual FPGA fabric to be evaluated under realistic, controllable, and repeatable channel conditions, including UE mobility and site-specific multi-path, without requiring an anechoic chamber or live RF front end. We detail the FPGA OFDM transmit/receive pipeline, the synchronization and data interface between the FPGA and the Sionna environment, and validation of signal quality under AWGN and ray-traced channel conditions, establishing this testbed as a platform for hardware-validated beamforming research.